Many high-speed signal-processing applications use finite impulse response (FIR) filters to perform high-speed linear filtering. Examples of such signal-processing applications include, but are not limited to, communications, video, radar, electronic warfare, and signal intelligence. Some applications use FIR filters in combination with other computational modules, such as multipliers, to implement nonlinear filters. In addition, different FIR filter designs can produce a wide variety of desired frequency responses.
In general, a FIR filter includes a series of delays, multipliers, and adders that cooperate to produce a filter output. For example, FIG. 1 shows a conventional transposed FIR filter 2 having a series of stages or taps 6 (here, four), an input line 10 for conveying input data, and an output line 14 for conveying the output data produced by the FIR filter 2. Each tap 6 includes a multiplier 18, an adder 22, and, with the exception of the last tap in the series, a delay 26. Input data pass concurrently to each multiplier 18 over the input line 10, and each multiplier 18 multiplies the input data by a coefficient (here, h3, h2, h1, or h0). The result produced by each multiplier 18 passes to the adder 22 of the same tap 6 as that multiplier 18. Each adder 22 produces a sum that passes to the delay 26 of the same tap 6 as that adder 22. Upon a subsequent clock cycle, the sum passes from the delay 26 to the adder 22 of the neighboring tap 6. For the last tap 6 in the series, the sum produced by the adder 22 corresponds to output data produced by the filter. In general, the filtering behavior of a FIR filter depends on the length of the filter (i.e., number of taps) and values of the coefficients. In this example, the output data is a function of four samples of input data. In the generating of the output data, the clock rate of the FIR filter is necessarily as fast as the input data sample rate.
Implementations of FIR filters for high-speed (i.e., data rate) applications often occur on application-specific processors because they are often capable of providing higher computational throughput and greater power efficiency than programmable processors. Technology for producing application-specific processors includes field-programmable gate arrays (FPGA), gate arrays, standard cells, and fully custom integrated circuits. Considerations taken in the design of such chips involve maximizing clock speed and computational throughput and minimizing die area and power consumption. In some instances, the input data rate required for the FIR filter exceeds the performance capability of the computational circuitry. In other instances, the computational circuitry can sustain the input data rate, but at the cost of consuming excessive power. Thus, there is a need for a FIR filter for linear and nonlinear filtering applications that can sustain the required input data rate without consuming excessive power.